1. Field of the Invention
This invention relates to a semiconductor device having a size equivalent to that of a semiconductor element, and to a manufacturing method therefor.
2. Description of the Related Art
The configuration of an example of a conventional chip-size semiconductor device 10 is described using FIG. 5.
Over a surface of a semiconductor element 12 on which electrode terminals 14 are formed, a passivation film 16 is formed, exposing the electrode terminals 14.
On the passivation film 16, an insulation coating 18 comprising an organic resin or the like is formed, exposing the electrode terminals 14 of the semiconductor element 12.
On the insulation coating 18 is formed (a) wiring pattern(s) 20, one end of which is electrically connected to an electrode terminal 14 of the semiconductor element 12, and the other end of wiring pattern(s) 20 forms a land 20a. Item 20b is a conductive site which forms a part of the wiring pattern 20 that connects the land 20a to the electrode terminal 14 of the semiconductor element 12.
On the surfaces of lands 20a, columnar electrodes 26 are arranged in an upright posture, and a sealing layer 28 is formed for sealing the wiring pattern 20, while exposing the top end surfaces of the columnar electrodes 26.
On the top end surfaces of the columnar electrodes 26 are formed plating layers 22 of nickel plating and gold plating, rendered successively.
Also, externally connecting terminals 24 are formed on the top end surfaces (that is, the surfaces of the plating layers 22) of the columnar electrodes 26, the top end surfaces being exposed out of the sealing layer 28.
In a semiconductor device 10 such as this, when the semiconductor device 10 is mounted on a mounting board (not shown), the wiring pattern 20 tends to be subjected to stress owing to the difference in the coefficients of thermal expansion between the semiconductor element 12 and the mounting board (a resin circuit board, for example).
Thereupon, the columnar electrodes 26 having an elongated shape are interposed between the externally connecting terminals 24 and the wiring pattern(s) 20, and the columnar electrodes 26 themselves absorb and ease that stress.
A summary of the manufacturing method for the semiconductor device 10 wherein a wiring pattern 20 is formed over the semiconductor element 12 as described above, is now described using FIGS. 6 to 10.
First, as diagrammed in FIG. 6, on the passivation film 16 that is on top of the semiconductor element 12, the insulation coating 18 made of a polyimide resin is formed, excluding the sites for the electrode terminals 14.
Next, as diagrammed in FIG. 7, a metal film 25 comprising an adhesive metal layer 25a made of titanium or chromium and a copper layer 25b is formed by sputtering so that the thicknesses of the layers 25a and 25b are on the order of approximately 0.05 to 0.2 xcexcm and approximately 0.5 xcexcm or so, respectively.
Next, as diagrammed in FIG. 8, a resist pattern 27 is formed in such a way that part of the copper layer 25b is left exposed for forming a wiring pattern (rewiring pattern) in the shape of groove, and, using this resist pattern 27 as a plating mask, and using the metal film 25 as a conductive layer, a plating film is formed by electrolytic copper plating on the metal film 25 to make the wiring pattern 20. The metal layer formed by this electrolytic copper plating constitutes the basic part of the wiring pattern 20.
After forming the wiring pattern 20, the resist pattern 27 is removed.
Next, as diagrammed in FIG. 9, a plating resist layer 29 is formed over the semiconductor element 12 on which the wiring pattern 20 is formed, light exposure and developing are performed, a hole 31 is formed in the resist layer 29, and the land 20a of the wiring pattern 20 is exposed.
Next, as diagrammed in FIG. 10, a plating film is formed by electroplating (copper, nickel, or the like) on the land 20a inside the hole 31, and the columnar electrode 26 is formed (to a height of approximately 100 xcexcm) by filling in the hole 31.
Furthermore, on the top end surface of this columnar electrode 26, a plating layer 22 comprising a nickel plating film and a gold plating film is formed. The plating layer 22 may also be a two-layer plating film wherein a nickel plating film and a palladium plating film are formed successively.
Next, the resist layer 29 is removed. Then, using the wiring pattern 20 as an etching mask pattern, etching is performed to remove the exposed metal film 25 (the copper layer 25b and adhesive metal layer 25a), thus making the wiring pattern(s) 20 independent.
In this manner, the insulation coating 18, the wiring pattern(s) 20, and the columnar electrodes 26 are formed on the semiconductor element 12 (FIG. 10).
Next, as diagrammed in FIG. 11, over the surface of the semiconductor element whereon the electrode terminals 14 are formed, the sealing layer 28 for sealing that semiconductor element surface is formed, using a resin having electrically insulative properties.
To describe this in greater detail, the sealing layer 28 is formed in such a way that the top end surface of the columnar electrodes 26 is exposed. Externally connecting terminals 24 such as solder balls, for example, are joined to the top end surfaces of the columnar electrodes 26 exposed out of the sealing layer 28.
The process steps up to this point are usually performed on a semiconductor wafer whereon a plurality of semiconductor elements are formed.
Then, last of all, the wafer is cut out into separate pieces according to respective semiconductor elements, so that the semiconductor device 10 diagrammed in FIG. 5 can be manufactured.
FIG. 13 is a perspective view of one example of a semiconductor device manufactured in this way.
FIG. 14 is a sectional side view of one example of a semiconductor device manufactured in this way. In this case, no columnar electrodes are installed.
FIG. 15 is a diagram of one example of a semiconductor device manufactured in this way, viewed from the top.
This figure is rendered so that the wiring pattern, etc. can be seen through the sealing layer.
In the semiconductor device 10 described above, since the coefficients of thermal expansion differ greatly between the semiconductor element 12 and the sealing layer 28 coating over and sealing the top of the surface of the semiconductor element 12 whereon the electrode terminals are formed (electrode terminal forming surface of the semiconductor element 12), it is considered to be necessary that the sealing layer 28 should not be easily peeled away from the adhesion surface thereof by the temperature fluctuation.
In the conventional semiconductor device 10, the sealing layer 28 is held onto the top of the electrode terminal forming surface of the semiconductor element 12 by two adhesive forces, namely the adhesive force between the sealing layer 28 and the insulation coating 18 formed over the electrode terminal forming surface of the semiconductor element 12, and the adhesive force between the wiring pattern 20 and the sealing layer 28.
Also, because the adhesive force between resin layers is the larger of these two adhesive forces, the greater part of the overall adhesive force is accounted for by the adhesive force between the insulation coating 18 formed of a polyimide resin or the like and the sealing layer 28.
However, as the number of the electrode terminals 14 on the semiconductor element 12 has been increasing, and the area of the wiring pattern(s) 20 formed over the electrode terminal forming surface has been increasing due to the miniaturization and the implementation of higher densities in recent years, the proportion of the exposed portion of the insulation coating 18 declines, resulting in a problem of a declined adhesive force of the sealing layer 28 over the electrode terminal forming surface as a whole.
Therefore, the present invention has been made to solve the above-described problems and aims at providing a semiconductor device and the manufacturing method therefor wherein a sealing layer shows excellent adhesive properties when it seals the electrode terminal forming surface of the semiconductor element.
Specifically, the invention in this application is as follows.
1. A semiconductor device comprising
a wiring pattern which is connected electrically, at one end thereof, to an electrode terminal formed on the electrode terminal forming surface of a semiconductor element, and forms, at the other end thereof, a land connected to an externally connecting terminal,
the wiring pattern being formed over the electrode terminal forming surface of that semiconductor element, and the wiring pattern having a side surface with an undercut portion.
2. The semiconductor device according to 1 above, wherein the wiring pattern is formed by laminating metal layers of a plurality of metals in a layered form, and the side surface of at least one metal layer A in that wiring pattern is formed as recessed inward in comparison with the side surface of a metal layer B formed on or above the metal layer A.
3. The semiconductor device according to 2 above, wherein the metal layer A is formed by copper plating, and the metal layer B is formed by nickel plating or nickel alloy plating.
4. A method for manufacturing a semiconductor device wherein a wiring pattern, one end of which is connected electrically to an electrode terminal formed on the electrode terminal forming surface of a semiconductor element, and the other end of which forms a land connected to an externally connecting terminal, is formed over the semiconductor, comprising the steps of:
forming the wiring pattern by laminating metal layers comprising a plurality of metals in a layered form; and
etching the side surface part of the wiring pattern.
5. The method of manufacturing a semiconductor device according to 4 above, wherein the wiring pattern is formed by laminating metal layers in a layered form with a nickel or nickel alloy plating layer on a layer formed by copper plating.
6. The method of manufacturing a semiconductor device according to 5 above, further comprising the steps of:
forming an insulation coating over the electrode terminal forming surface, exposing the electrode terminal;
forming a metal film on the insulation coating and the electrode terminal;
forming a resist pattern on the metal film in such a way that sites for forming the wiring pattern are exposed;
removing the resist pattern after forming that wiring pattern by laminating layers; and
etching and removing the metal film that is exposed, using that wiring pattern as a mask pattern.
7. The method of manufacturing a semiconductor device according to 6 above, wherein the metal film is formed on a metal film of chromium by laminating a metal film of copper in a layered form.
It was discovered that, when the side surface portion of the wiring pattern described above has an undercut portion, the adhesive properties of the sealing layer 28 can be greatly improved. By xe2x80x9cundercutxe2x80x9d here, it is meant that a side surface of the wiring pattern 20 is structured so that a lower portion thereof is recessed in comparison with an undercut portion thereover, as diagrammed in FIGS. 12A, 12B, and 12C. The effect on the present invention is thought to be obtained due to a so-called anchor effect that is produced by the resin which fills in the recess and thus opposes the xe2x80x9cforce pulling upwardxe2x80x9d, when a force is developed to pull the sealing layer 28 upward as diagramed in FIGS. 12A, 12B, and 12C.
Such an undercut structure may be prepared by any known method whatever. It is also possible, for example, to effect plating so that the uppermost plating layer overhangs, as diagrammed in FIG. 12A.
Also, in a case where, for example, the wiring pattern comprises a metal layer X (exemplified in FIG. 12B) consisting of a metal that is readily eroded by wet etching and a metal layer Y (exemplified in FIG. 12B) formed thereover that consists of a metal this is highly resistant to erosion by wet etching, it is possible to form an undercut such as that diagrammed in FIG. 12A by performing wet etching to etch the side surface portion of X relatively more than the side surface portion of the Y layer. This method is technically simple and is to be preferred.
Needless to say, laminating a metal layer is not an indispensable condition for forming the undercut.
Moreover, in cases where the wiring pattern consists of a plurality of metal layers, it is preferable that the metal layer that will be the basic part of the wiring pattern be formed by copper plating, and that the metal layer formed thereon be formed by nickel plating or nickel alloy plating for the purpose of easier undercut formation.
In that case, it is not always necessary that the metal layer that is on or above the metal layer to be etched to a greater extent be immediately located on top of the very metal layer etched to a greater extent, but the effectiveness of the undercut (effectiveness of the recess) is more greatly manifested with the structure wherein the metal layer is immediately on top of the very metal layer etched to a greater extent. This is therefore to be preferred.
It is noted that, as described in the foregoing, when fabricating a semiconductor device, a process step is commonly incorporated for removing, by etching, the exposed electrically conductive metal film, and it sometimes happens during the process that the cross section of the metal film will be more recessed than the cross section of the wiring pattern as a mask pattern for etching, resulting in producing an undercut structure. However, such an undercut makes little contribution to improving the adhesive properties of the sealing layer 28, and it is important to have an undercut on the wiring pattern itself.
The reason for this is not clear, but it is conjectured that the reason is that, with the metal film having a thickness of about 0.5 to 0.7 xcexcm, it is difficult for the sealant itself to enter the recess, and that adequate rigidity cannot be secured to oppose a pulling force from above, even if it has entered the recess.
The present invention also includes the methods 4 to 7 noted above.
More specifically, as per the foregoing, etching of the side surface portions of the layered metals of the wiring pattern is a preferable method. Dry etching or wet etching may be applied. Wet etching is preferred since a difference in etching speed between metals can easily be effected by the method.
It is preferable that the metal film noted above be formed by laminating a metal film of copper in a layered form on a metal film of chromium.
As the wiring patterns based on the present invention provide a great effect, it will be effective, in the sense of enhancing the adhesive properties of the sealing layer, to take a positive measure of installing a wiring pattern as a dummy wiring, at a location where there is no functional need for rewiring, and at a location where the number (density) of the original wiring patterns is small, for the purpose of obtaining the anchor effect as the object of the present invention. It is noted, in that case, there is naturally no need to connect those wiring patterns to the semiconductor electrode terminals or externally connecting terminals.